The invention relates to a sample and hold circuit architecture that reduces pedestal error, offset error, droop error, and linearity errors, and relates especially to a plurality of such sample and hold circuits having inputs multiplexed to the output of a single DAC or other analog signal source. The invention also relates to a plurality of such sample and hold circuits having outputs multiplexed to the input of a single ADC.
It is well known that a single DAC, multiple sample/hold conversion circuit can have a number of advantages, including reduced integrated circuit die size and cost, improved channel-to-channel matching, improved integrated circuit yield, and reduced component trimming time, testing time, and cost. Despite these advantages of single DAC, multiple sample/hold conversion circuit, performance limitations on the capabilities of known sample/hold circuits have prevented more widespread use thereof. Specifically, known sample/hold circuits are subject to switching transient errors, pedestal errors, offset errors, and droop errors totaling approximately 50 millivolts, which limits the use of such known sample/hold circuits in single DAC, multiple sample/hold circuits to approximately 10 bit accuracy. Also, hold times of only a few microseconds are typical for known sample/hold circuits, and such short hold times necessitate use of high speed DAC for a single DAC, multiple sample/hold conversion circuit applications. The short hold times also necessitate a high refresh rate, which greatly increases power consumption, and also limits the number of sample/hold outputs that can be provided for the single high-speed DAC. Furthermore, the required high refresh rate greatly increases the number of transient impulses that appear at the sample/hold outputs per unit of time, and this increases the amount of switching noise and necessitates more complex filtering of the sample/hold outputs.
FIG. 1 illustrates what is believed to the closest prior art. Referring to FIG. 1, a single DAC, multiple sample/hold conversion circuit 1 includes a DAC 8228 digital-to-analog converter 2 (available from Analog Devices Inc.) having its output coupled to the input of an SMP08 circuit 3 (also available from Analog Devices Inc.) including multiple sample/hold circuits. Each of the eight sample/hold circuits in block 3 includes a switch 6, a hold capacitor 8, and an output amplifier 7. Typically, one terminal of the switch 6 is connected to the (+) input of the operational amplifier 7 and to one terminal of a hold capacitor 8. The other terminal of each switch 6 is connected to the output 5 of DAC 2. An address decoder 4 controls which one of switches 6-1,2 . . . 8 is closed to charge the corresponding hold capacitor 8-1,2 . . . 8 to the output voltage of DAC 2. The digital inputs of DAC 2 can receive digital input signals from any of a number of sources, and a corresponding address is applied to the input of address decoder circuit 4 to determine which sample/hold circuit in block 3 samples and stores the analog output into which the present digital input is converted. The output of each amplifier 7 provided as feedback to the (xe2x88x92) input of that amplifier to thereby configure the amplifier as a unity gain buffer.
The prior art single DAC, multiple sample/hold conversion circuit 1 of FIG. 1 has several shortcomings. One is that there is no cancellation of pedestal errors which appear as an offset of the output voltage due to switching charge that is distributed onto the hold capacitor 8 of a sample/hold circuit when its input switch 6 is opened. Another shortcoming is that charge on the hold capacitor 8 is slowly discharged through parasitic leakage paths during the hold mode of each sample/hold circuit, causing xe2x80x9cdroopxe2x80x9d of the output voltages (on conductors 9-1,2 . . . 8) of the sample/hold circuit 3 during their respective hold modes. A third shortcoming of the prior art single DAC, multiple sample/hold circuit 1 of FIG. 1 is that there is no mechanism for reducing linearity errors due to non-linearity of the output amplifier of the sample/hold circuit. Note that in the prior art sample/hold circuits the settling time and accuracy are limited by the amount of time required to fully charge the hold capacitor, and the voltage drop across the sampling switch has fallen to zero by the time the hold capacitor is fully charged. In the prior art sample/hold circuits, errors related to offset, linearity, and input common mode of the op-amp are translated directly to the output of the sample/hold circuit.
Another shortcoming of the prior art single DAC, multiple sample/hold conversion circuit of FIG. 1 is that channel-to-channel crosstalk and hold time reduction result from the large range of signals that appear at the DAC output 5 in FIG. 1 and at the input of each sample/hold xe2x80x9cchannelxe2x80x9d during its hold mode while other digital input signals are converted by DAC 2 during the acquire mode of the other channels. For example, sample/hold output 9-1 can be xe2x80x9cprogrammedxe2x80x9d to be +2.5 volts by a particular digital input converted by DAC 2 such that hold capacitor 8-1 is charged to +2.5 volts, and then sampling switch 6-1 is turned off. Sample/hold output 9-2 then is programmed to be xe2x88x922.5 volts by another digital input digitized by DAC 2 such that hold capacitor 8-2 is charged to xe2x88x922.5 volts and sampling switch 6-2 is turned off. While the analog value for the second channel including sample/hold output 9-2 is being xe2x80x9cacquiredxe2x80x9d, i.e., is being sampled and held, sampling switch 6-1 has a voltage of +5 volts across it, which causes a significant corresponding leakage current that reduces the charge on hold capacitor 8-1, contributing to the voltage droop of sample/hold output 9-1 in the positive direction during the time that the analog value to be output on conductors 9-2 is being acquired. Thus, opposite polarities of the two sample/hold output voltages result in opposite polarity output voltage droop contributions, and each sample/hold output voltage is affected by the values of the other sample/hold outputs in a sort of pseudo-random way. Therefore, the output voltage droop of each sample/hold circuit during its hold mode is unpredictable and its slope varies depending on the values and acquisition timing of the other sample/hold outputs.
Thus, there is an unmet need for an improved sample and hold circuit architecture that provides reduced pedestal error, offset error, droop error, and linearity error and does not exhibit channel-to-channel interaction.
There also is an unmet need for an improved sample and hold circuit architecture which provides reduced pedestal error, offset error, droop error, and linearity error and does not exhibit channel-to-channel interaction in a single DAC, multiple sample/hold conversion circuit including a plurality of such sample and hold circuits having inputs multiplexed to the output of a single DAC.
There also is an unmet need for an improved sample and hold circuit architecture which provides reduced pedestal error, offset error, droop error, and linearity error and does not exhibit channel-to-channel interaction in a single DAC, multiple sample/hold conversion circuit including a plurality of such sample and hold circuits having inputs multiplexed to the output of a single DAC and also provides rejection of various common-mode noise signals.
There also is an unmet need for an improved sample and hold circuit architecture which provides reduced pedestal error, offset error, droop error, and linearity error in a single ADC, multiple sample/hold conversion circuit including a plurality of such sample and hold circuits having outputs multiplexed to the input of a single ADC.
Accordingly, it is an object of the invention to provide an improved sample and hold circuit architecture which provides reduced pedestal error, offset error, droop error, and linearity error.
It is another object of the invention to provide an improved sample and hold circuit architecture which provides reduced pedestal error, offset error, droop error, and linearity error and which also provides rejection of common-mode noise.
It is another object of the invention to provide an improved sample and hold circuit architecture which provides reduced pedestal error, offset error, droop error, and linearity error in a single DAC, multiple sample/hold conversion circuit including a plurality of such sample and hold circuits having inputs multiplexed to the output of a single DAC.
It is another object of the invention to provide an improved sample and hold circuit architecture which provides reduced pedestal error, offset error, droop error, and linearity error in a single ADC, multiple sample/hold conversion circuit including a plurality of such sample and hold circuits having outputs multiplexed to the input of a single ADC.
It is another object of the invention to provide a programmable, multi-function integrated circuit including an improved sample and hold circuit architecture which provides reduced pedestal error, offset error, droop error, and linearity error in single DAC, multiple sample/hold conversion circuitry including a plurality of such sample and hold circuits having inputs multiplexed to the output of a single DAC and in a plurality of such sample and hold circuits having outputs multiplexed to the input of a single ADC.
Briefly described, and in accordance with one embodiment thereof, the invention provides a sample/hold circuit including an output amplifier (70), a first hold capacitor (81) coupled to a first input (+) of the output amplifier (70) and a first terminal of a first sampling switch (60), a second hold capacitor (80) having a first terminal coupled to a second input (xe2x88x92) of the output amplifier (70) and to a first terminal of a second sampling switch (61) and a second terminal coupled to an output (9) of the output amplifier (70), and a feedback element coupled to the output (9) of the output amplifier (70). An operational amplifier (11) includes a first input (+) for receiving an analog input voltage, a second input (xe2x88x92), a first output (19A) coupled to a second terminal of the first sampling switch (60), and a second output (19B) coupled to a second terminal of the second sampling switch (61), the second input (xe2x88x92) of the operational amplifier (11) being coupled to the feedback element. An element is coupled to control elements of the first and second sampling switches for conducting a switch control signal for closing the first and second sampling switches to cause the sample/hold circuit to sample the analog input voltage by charging the first and second hold capacitors to voltages on the first and second outputs of the operational amplifier, respectively, and for opening the first and second sampling switches to cause the sample/hold circuit to hold the sampled analog input voltage.
In another embodiment, the invention provides a multiple sample/hold circuit including a plurality of sample/hold circuits (90) each including an output amplifier (70), a first hold capacitor (81) coupled to a first input of the output amplifier and a first terminal of a first sampling switch (60) and a second terminal coupled to an output (9) of the output amplifier, and a feedback switch (16) having a first terminal coupled to the output of the output amplifier. An operational transconductance amplifier (11) has first (+) and second (xe2x88x92) inputs, a first output connected to a second terminal of the first switch (60), the second input (xe2x88x92) of the operational transconductance amplifier being coupled to a second terminal of the feedback switch (16). A control circuit applies a selected analog signal (18A) to the first input of the operational transconductance amplifier and receives an address input (17) and selects one of a plurality of switch control buses (14) in response to the address input. Each switch control bus is coupled to control the feedback switch (16), first switch (60), and second switch (61) of a corresponding sample/hold circuit (90), the control logic circuit (15) producing switch controls signals on the selected switch control bus to control the feedback switch (16) and first switch (60) of the corresponding sample/hold circuit (90).
In the described embodiment, the sample/hold circuits (90) each include a first hold capacitor (81) coupled to a first input (+) of the output amplifier and a first terminal of a first sampling switch (60), a second hold capacitor (80) having a first terminal coupled to a second input (xe2x88x92) of the output amplifier and to a first terminal of a second sampling switch (61) and a second terminal coupled to an output (9) of the output amplifier, and a feedback switch (16) having a first terminal coupled to the output of the output amplifier. The control logic circuit (15) producing switch controls signals on the selected switch control bus to control the second switch (61) of the corresponding sample/hold circuit (90). Each of the first (60) and second (61) sampling switches includes first (69) and second (66) N-channel transistors each having a gate connected to a control signal (S) and first (71) and second (65) P-channel transistors each having a gate coupled to a logical complement ({overscore (S)}) of the control signal, the first N-channel transistor (69) having a first electrode coupled to the second terminal of the first sampling switch and a second electrode coupled to a first electrode of the second N-channel transistor (66), a body electrode of the first N-channel transistor (69) being coupled to a low supply voltage (VEE), a second electrode of the second N-channel transistor (66) being coupled to the first terminal of the first sampling switch, the first P-channel transistor (71) having a first electrode coupled to the second terminal of the first sampling switch and a second electrode coupled to a first electrode of the second P-channel transistor (65), a second electrode of the second P-channel transistor (65) being coupled to the first terminal of the first sampling switch, a body electrode of the first P-channel transistor (71) being coupled to a high supply voltage (VCC).
In one described embodiment, control circuitry (15) includes digital data control circuitry for routing a digital data input signal (33) to an input (13A) of a digital-to-analog converter (2) to cause the digital-to-analog converter to produce the selected analog signal (18A) signal on the first input (+) of the operational transconductance amplifier (11). In another described embodiment, the control circuitry (15A) includes a first demultiplexer (96) for switching a selected analog signal onto the first input (+) of the operational transconductance amplifier in response to the address input and a second demultiplexer (27) for switching the output of a selected sample/hold circuit to an input of the analog-to-digital converter in response to the address input. The control circuitry (15) includes digital data control circuitry for routing a digital data input signal (33) to an input (13A) of a digital-to-analog converter (2) to cause the digital-to-analog converter to produce the selected analog signal (18A) signal on an input of the first demultiplexer (96). In one described embodiment, the control circuitry (15) includes register circuitry (40) coupled to receive a digital output signal produced by the analog-to-digital converter (99) and circuitry programmable to refresh a particular sample/hold circuit (70) by applying the digital output signal in the register circuitry (40) to the digital input of the digital-to-analog converter (2) and switching the output of the digital-to-analog converter through the first demultiplexer (96) to the first (+) of the operational transconductance amplifier.